There has been a priority encoder which outputs output data representing a bit position at which “0” or “1” appears first from the most significant bit of the binary input data.
Conventionally, a parity bit has not been attached to output data (priority encoder result) from the priority encoder. Various methods have been proposed for parity generation. (e.g., see Patent Reference 1 below.)
However, a demand for detailed error detection has arisen, and with the intention of error detection, high-reliability processors attach parity bits for arithmetic circuits, which have not been the objects of the detection. As a part of the purpose, it is desired that a parity bit attached to output data from a priority encoder (exemplified by a leading zero counter which is used in shift amount calculation for data normalization and which counts the number of zero bits of input data from the most significant bit).
As a method for generating a parity of output data from a priority encoder, the first and second methods respectively shown in FIGS. 14 and 15 are easily conceived.
The below explanation assumes that a priority encoder outputs, as output data, the position (bit position) of the first “0” of binary input data from the most significant bit.
A parity bit is a signal which indicates whether the number of “0s” or “1s” included in data is an even number or an odd number for error detection for the data. The following example provides that, if the number of “1s” included in output data from a priority encoder is an odd number, the parity bit is “1”.
For the first method, alogical EXOR (Exclusive OR) circuit 102 is disposed on the output side of priority encoder 100 and a parity of output data from priority encoder 100 is generated by calculating the exclusive OR of the same output data, as shown in FIG. 14.
For the second method, as shown in FIG. 15, a parity generating circuit 105 including a number of logical AND circuits 103 (however appears only logical AND circuits 103-0 to 103-2 in the drawing) and a single OR gate 104 generates a parity of output data from a priority encoder (not shown) on the basis of the data input (input signals Z0-Zn) into the priority encoder.
Specifically, a number of logical AND circuits 103 are arranged in parallel, and input data in increments of two bits are sequentially input into the logical AND circuits 103 from the top logical AND circuit (here, logical AND circuit 103-0). Each logic circuit is to output “1” only when the input data is in a particular pattern. The number of logical AND circuits 103 depends on the number of bits of input data and the number of bits of the increment to each logic circuit.
In other words, into the top logical AND circuit 103-0, input data Zn and the inverse of input data Zn-1 are input. Thereby “1” is output only when input data Zn is “1” and input data Zn-1 is “0”.
In addition to input data Zn and input data Zn-1, input data Zn-2 and the inverse of input data Zn-3 are input into logical AND circuit 103-1. Thereby, “1” is output from logical AND circuit 103-1 only when input data Zn to Zn-2 are all “1” and the input data Zn-3 is “0”.
Further, input data Zn-4 and the inverse of input data Zn-5 are input into logical AND circuit 103-2 in addition to input data Zn to Zn-3, so that “1” is output from logical AND circuit 103-2 only when input data Zn to Zn-4 are all “1” and input data Zn-5 is “0”.
Into the lowest logical AND circuit 103, all the input data Zn-Z0 are input, and the logical product is calculated.
In succession, in parity generating circuit 105, logical OR circuit 104 calculates the logical sum of all the output from these logical AND circuits 103 and outputs the result of the calculation as the parity bit.    Patent Reference 1: Japanese Laid-open Patent Publication No. 2000-20332.